Desain Layout 1-Stage ADC Pipeline 80Msps dengan Mentor Graphics 0,35µm untuk Aplikasi Kamera Kecepatan Tinggi

Hamzah Afandi, Erma Triawati Ch., Atit Pertiwi

Abstract


Design layout 1-stage pipeline is part of the 8-stage pipeline 80 Msps ADC. Layout 1-stage pipeline consists of 3 units : op-amp, switch capacitor, precision comparator with latch. Pipeline ADC works gradually and requires synchronization of digital output 8 stage by using a unit delay circuit (D-FF). Pipeline ADC requires pulse rate (clock) generator to support its work. Units OP-AMP transconductance CMOS components designed with the correct specification ADC applications with capacitive loads, with a large input impedance and minimize noise. The precision comparator has Vos (offset voltage) approximately equal to 0V. The capacitor switch designs use NMOS switch as a switch for the sampling and multiplying. In the sampling phase and multiplying processes, the ADC requires a clock pulse with a non-intersect mode (lapping). The width of non-overlapping period was adjusted to the time of constance in the sampling process and multiplying. The total number of each pulse period equal to 12.5 ns or equal to the frequency of 80MHz. In the 1-stage layout an additional correction capacitor was required to correct residual voltage. The total area of the layout 1-stage pipeline ADC is 1-bit 200 μm x 98μm.

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DOI: https://doi.org/10.17529/jre.v10i2.141

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